Work in a team environment to develop and maintain custom/analog IC design flows. This position will provide exposure to following aspects of IC design on modern foundry technologies:
- Schematic Capture
- Custom layout
- Spice and mixed signal simulation
- Physical verification DRC/LVS
- Parasitic extraction
- EDA tool environment and licensing
- Familiar with Cadence design environment including schematic simulation and layout verification tools
- Shell Scripting and Cadence Skill experience are a plus
- Familiar with Linux
- Experience with Python
- Understanding of Semiconductor Device Physics, Mixed Signal circuit/layout principles and techniques
- Familiarity with hardware description language such as Verilog etc.
- Candidate must be pursuing Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field.